1. Field of the Invention
This invention relates to a method for testing electrical connectivity on a chip. More particularly, this invention relates to a method for testing electrical connectivity between conductive structures on a chip that has no active electrical devices.
2. Background and Summary
Integrated circuit chips generally include layers of conductive and nonconductive materials, sandwiched together. The chips generally have a number of probes or connectors that connect the chip to external devices. Each layer may include many elements, including active electrical devices (such as transistors), capacitors, inductors, conductive wire runs, conductive vias through the layer, and the like. Combinations of these elements may be interconnected to electrically connect various probes to one another.
Integrated circuit chips must be tested for design flaws before production. For example, electrical connections between various probes on a chip must be tested to determine if any unwanted short or open circuits exist between the probes.
Thus, methods have been developed for testing electrical connectivity on integrated circuit chips. Computerized testing methods exist for chips with layers that include active electrical devices, capacitors, and inductors.
Chips have recently been developed, however, that have no active electrical devices and no capacitors or inductors. These chips, known generally as Magnetic Memory Design ("MMD") chips, are presently used for data storage. An MMD chip, like conventional chips, has probe pads that connect the MMD chip to external devices. The probe pads are interconnected by a network of conductive structures, including polygonal structures and wire runs, which are located on stacked conductive layers. The conductive layers are generally separated by nonconductive (or insulating) layers.
Conventional MMD chips are not highly complex. They have only a few layers and a few conductive structures on each layer. As a result, the electrical connectivity between probe pads and other conductive structures on conventional MMD chips has been tested by hand, with little risk of error.
Recently, however, highly-complex MMD chips have been developed that have many conductive layers, many small conductive structures formed on those layers, and many probe pads. Consequently, conventional hand-testing for electrical connectivity is unreliable, impractical, and uneconomical for these new MMD chips. In addition, computerized methods for testing chips that have active electrical devices, capacitors, and/or inductors do not work for MMD chips. Those methods rely on the existence of at least some active electrical devices, capacitors, and/or inductors on the chip. The absence of such devices on MMD chips causes conventional computerized testing methods to register short circuits between electrically connected probe pads and other conductive structures.
Accordingly, the inventors recognized the need for a method to test the electrical connectivity on chips that have no active electrical devices and/or no capacitors or inductors.
It is an object of the present invention to provide a method for testing and verifying electrical connections between conductive structures on a chip consisting of a network of conductive structures.
It is a further object of the present invention to provide a method for constructing a linked path of conductive structures between probe pads on a chip with no active electrical devices and/or no capacitors or inductors.
It is yet another object of the present invention to test the designs of a chip having no active electrical devices and no capacitors or inductors to ensure that probe pads are correctly linked on each layer and between layers of the chip.
In accordance with the present invention, a method is provided for determining electrical connectivity on a chip. The method includes providing a chip devoid of active electrical devices and devoid of capacitors and inductors and having multiple layers and multiple conductive structures. The method further includes determining the layer on which each conductive structure is located, determining whether any conductive layer connections exist between the plurality of layers, and determining which conductive structures are electrically connected.
Another embodiment of the present invention is a method for testing electrical connections between conductive structures on a chip having multiple layers. The conductive structures include polygonal conductive structures, each of which is located on a known layer. The method includes determining, for each polygonal conductive structure, a set of line segments defining its perimeter. The method further includes determining conductive layer connections between each of the layers, and determining, for each polygonal conductive structure, points of intersection between the set of line segments defining the perimeter of that structure and the set of line segments of all other structures on the chip. The method also includes testing electrical connections between conductive structures using the conductive layer connections and the points of intersection.
Another embodiment of the present invention is a method for finding electrical short circuits on a microchip having electrically interconnected conductive structures. Each conductive structure has a perimeter, and the microchip has multiple layers. The conductive structures include vias between at least some of the layers. The method includes determining a set of vertices along the perimeter of each conductive structure. The method further includes determining, for each conductive structure, a set of line segments connecting its vertices and thereby defining its perimeter. The method also includes determining points of intersection between the set of line segments for each conductive structure to locate overlapping conductive structures, and locating the vias by determining the conductive structures, if any, that are contained within the set of line segments of another conductive structure. Finally, the method includes checking continuity of an electrical path between conductive structures using the points of intersection and the vias.
The details of the preferred embodiment of the present invention are set forth in the accompanying drawings and the description below. Once the details of the invention are known, numerous additional innovations and changes will become obvious to one skilled in the art.